american microsystems, inc. november 2000 this document contains information on a new product. specifications and information herein are subject to change without notice . 11.10.00 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 FS6058-01 FS6058-01 FS6058-01 FS6058-01 lvpecl to hcsl/lvttl motherboard clock driver ic lvpecl to hcsl/lvttl motherboard clock driver ic lvpecl to hcsl/lvttl motherboard clock driver ic lvpecl to hcsl/lvttl motherboard clock driver ic preliminary information preliminary information preliminary information preliminary information 1.0 features ? distributes one differential lvpecl reference clock to six differential hcsl clock pairs and two single- ended lvttl mref clocks ? hcsl current levels controlled by iref current reference and mult_0:1 current multiplier pins ? host clock frequency division selected via the sel_a, sel_b, and sel_u input signals ? active-low pwr_dwn# signal disables all outputs ? tristate output control via sel_t facilitates board testing ? available in a 48-pin ssop and tssop figure 1: block diagram pwr_dwn# fs6058 current adjust iref mult_0:1 4 sel_t sel_a sel_b sel_u pecl_p pecl_n divider control vss_h vdd_h host_p2:5 host_n2:5 vss_h vdd_h host_p1,6 host_n1,6 vss_m vdd_m mref_p mref_n figure 2: pin configuration 1 48 2 3 4 5 6 7 8 47 46 45 44 43 42 41 vdd vdd_r vss pecl_n vss_r vss vss_h vdd 9 10 11 12 13 14 15 16 vdd vss_l sel_t mult_0 mult_1 vss_l vdd sel_a 17 18 19 20 21 22 23 sel_b mref_p mref_n 40 39 38 37 36 35 34 33 vss_h host_n1 vss_h host_p2 32 31 30 29 iref host_p6 host_n6 vss_h 24 FS6058-01 vdd_l sel_u host_p5 host_p1 vdd_h 25 26 27 28 vdd_i pecl_p vss_m vss_i host_n2 vdd_l pwr_dwn# vdd_h host_n5 vdd_h host_n4 host_p4 host_n3 host_p3 vdd_h vdd_m pair 1 pair 2 pair 3 pair 4 pair 5 pair 6 table 1: divider and power-down control control inputs clock outputs (mhz) pwr_ dwn# sel_ t sel_ a sel_ b sel_ u host_p1 host_n1 host_p2 host_n2 host_p3 host_n3 host_p4 host_n4 host_p5 host_n5 host_p6 host_n6 mref_p mref_n 1 0 0 0 0 pecl 2 pecl 2 pecl 2 pecl 2 pecl 2 pecl 2 pecl 4 1 0 0 0 1 tristate pecl 2 pecl 2 pecl 2 pecl 2 tristate pecl 4 1 0 0 1 0 pecl 4 pecl 2 pecl 2 pecl 2 pecl 2 pecl 4 pecl 4 1 0 0 1 1 pecl 4 pecl 4 pecl 4 pecl 4 pecl 4 pecl 4 pecl 4 1 0 1 0 0 pecl pecl pecl pecl pecl pecl pecl 4 1 0 1 0 1 tristate pecl pecl pecl pecl tristate pecl 4 1 0 1 1 0 pecl 2 pecl pecl pecl pecl pecl 2 pecl 4 1 0 1 1 1 pecl 2 pecl 2 pecl 2 pecl 2 pecl 2 pecl 2 pecl 2 1 1 x x x tristate tristate tristate tristate tristate tristate tristate host_p1 = 2 iref host_p2 = 2 iref host_p3 = 2 iref host_p4 = 2 iref host_p5 = 2 iref host_p6 = 2 iref mref_p = high 0xxxx host_n1 = tristate host_n2 = tristate host_n3 = tristate host_n4 = tristate host_n5 = tristate host_n6 = tristate mref_n = low
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 2 FS6058-01 FS6058-01 FS6058-01 FS6058-01 lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl motherboard clock driver motherboard clock driver motherboard clock driver motherboard clock driver ic ic ic ic preliminary information preliminary information preliminary information preliminary information table 2: pin descriptions ai = analog input; ao = analog output; di = digital input; di u = input with internal pull-up; di d = input with internal pull-down; dio = digital input/output; do = digital output; p = power/ground; # = active-low pin pin type name description supply 44 host_n1 45 ao host_p1 differential output pair 1 outside pair 41 host_n2 42 ao host_p2 differential output pair 2 38 host_n3 39 ao host_p3 differential output pair 3 35 host_n4 36 ao host_p4 differential output pair 4 32 host_n5 33 ao host_p5 differential output pair 5 inside pairs 29 host_n6 30 ao host_p6 differential output pair 6 outside pair current-steering differential current-mode (hcsl) outputs provided for clocking the cpu. the output drive current is established via a reference current at iref and a multiplying factor set by mult_0:1 vdd_h 27 ai iref a fixed precision resistor from this pin to ground provides a reference current used for the differential current-mode host clock outputs vdd_i 9domref_n single-ended clock (180 out of phase with mref_p) provided as a reference clock to a memory clock driver 8 do mref_p single-ended clock in a pair of outputs reference clock to a memory clock driver vdd_m 17, 18 di mult_0 mult_1 the logic setting on these two pins selects the multiplying factor of the iref reference current for the host pair outputs vdd_l 5 pecl_n lvpecl input (complementary) 4 ai pecl_p differential input lvpecl input (true) vdd_r 24 di pwr_dwn# asynchronous active-low lvttl power-down signal forces mref outputs low, tristates host_n outputs, and drives host_p output currents to 2xiref vdd_i 21 di sel_a used in conjunction with sel_b and sel_u to select desired output frequencies 22 di sel_b used in conjunction with sel_a and sel_u to select desired output frequencies 16 di sel_t active high input tristates all outputs 23 di sel_u used in conjunction with sel_a and sel_b to select desired output frequencies vdd_l 2, 11, 14, 48 p vdd 3.3v core power supply 28, 34, 40, 46 p vdd_h 3.3v power supply for the differential host clock outputs 25 p vdd_i 3.3v power supply for iref current reference input 13, 19 p vdd_l 3.3v power supply for logic input pins 7 p vdd_m 3.3v power supply for mref clock outputs 3 p vdd_r 3.3v power supply for pecl reference clock inputs 1, 12 p vss core ground 31, 37, 43, 47 p vss_h ground for the differential host clock outputs 26 p vss_i ground for iref current reference input 15, 20 p vdd_l ground for logic input pins 10 p vss_m ground for the mref clock outputs 6 p vss_r ground for pecl inputs -
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 3 FS6058-01 FS6058-01 FS6058-01 FS6058-01 lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl motherboard clock driver motherboard clock driver motherboard clock driver motherboard clock driver ic ic ic ic preliminary information preliminary information preliminary information preliminary information 2.0 host buffer current control the current supplied at the host outputs is controlled by two parameters: (1) the value of the programming resistor from the iref pin to ground (vss), and (2) the multiplier factor determined by the logic setting of the mult_0 and mult_1 pins. the host output current is a mirrored and scaled copy of the reference current flowing through the programming resistor on the iref pin. the voltage that appears at the iref pin is one-third of the voltage at the vdd_i pin. therefore, the reference current is iref ref r i ? ? ? ? ? ? = vdd_i 3 1 . the mirrored reference current can be increased by adding one or more copies of the mirror current together. the additional current is controlled by the logic settings on the mult_0 and mult_1 pins. table 3: current multiplier mult_0 mult_1 multplier 00 i o = 5 i ref 01 i o = 6 i ref 10 i o = 4 i ref 11 i o = 7 i ref table 4: host current selection program resistor reference current current multiplier trace impedance output voltage 60 ? 0.71v 475 ? (1%) 2.32ma i o = 5 i ref 50 ? 0.59v 60 ? 0.85v 475 ? (1%) 2.32ma i o = 6 i ref 50 ? 0.71v 60 ? 0.56v 475 ? (1%) 2.32ma i o = 4 i ref 50 ? 0.47v 60 ? 0.99v 475 ? (1%) 2.32ma i o = 7 i ref 50 ? 0.82v 30 ? 0.75v 221 ? (1%) 5ma i o = 5 i ref 25 ? 0.62v 30 ? 0.90v 221 ? (1%) 5ma i o = 6 i ref 25 ? 0.75v 30 ? 0.60v 221 ? (1%) 5ma i o = 4 i ref 25 ? 0.50v 30 ? 1.05v 221 ? (1%) 5ma i o = 7 i ref 25 ? 0.84v note: shaded row indicates the primary system configuration table 5: host buffer clock outputs high drive current (ma) at primary system configuration output voltage (v) min. typ. max. 3.30 0.00 0.00 0.00 3.14 -3.03 -4.22 -5.76 2.97 -5.66 -7.68 -9.86 2.81 -7.87 -10.30 -11.85 2.64 -9.67 -11.91 -12.45 2.48 -11.05 -12.56 -12.84 2.31 -11.98 -12.85 -13.16 2.14 -12.52 -13.07 -13.45 1.98 -12.77 -13.26 -13.72 1.81 -12.91 -13.42 -13.96 1.65 -12.99 -13.54 -14.17 1.48 -13.04 -13.64 -14.36 1.32 -13.07 -13.70 -14.52 1.15 -13.08 -13.73 -14.64 0.99 -13.09 -13.75 -14.71 0.82 -13.11 -13.76 -14.74 0.66 -13.12 -13.78 -14.76 0.49 -13.13 -13.79 -14.78 0.33 -13.13 -13.80 -14.80 0.16 -13.14 -13.81 -14.82 0.00 -13.15 -13.82 -14.83 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 0123 output voltage (v) output current (ma) 30? 50? 90? max voh data in this table represents nominal characterization data only
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 4 FS6058-01 FS6058-01 FS6058-01 FS6058-01 lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl motherboard clock driver motherboard clock driver motherboard clock driver motherboard clock driver ic ic ic ic preliminary information preliminary information preliminary information preliminary information 3.0 electrical specifications table 6: absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. exposure to maximum rati ng conditions for extended conditions may affect device performance, functionality, and reliability. parameter symbol min. max. units supply voltage (v ss = ground) v dd v ss -0.5 7 v input voltage, dc v i v ss -0.5 v dd +0.5 v output voltage, dc v o v ss -0.5 v dd +0.5 v input clamp current, dc (v i < 0 or v i > v dd )i ik -50 50 ma output clamp current, dc (v i < 0 or v i > v dd )i ok -50 50 ma storage temperature range (non-condensing) t s -65 150 c ambient temperature range, under bias t a -55 125 c junction temperature t j 125 c lead temperature (soldering, 10s) 260 c input static discharge voltage protection (mil-std 883e, method 3015.7) 2 kv caution: electrostatic sensitive device permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. table 7: operating conditions parameter symbol conditions/description min. typ. max. units core (vdd) 3.135 3.3 3.465 v supply voltage v dd clock buffers (vdd_h, vdd_i, vdd_m, vdd_r, vdd_l) 3.135 3.3 3.465 v operating temperature range t a 070c reference frequency range mhz input rise/fall time 200 ps input duty cycle 40 60 % input high-level voltage 2.135 2.420 v input low-level voltage required lvpecl signalling parameters 1.490 1.825 v load capacitance c l mref_p, mref_n 10 30 pf load resistance r l host_p1 to host_p6, host_n1 to host_n6 20 105 ?
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 5 FS6058-01 FS6058-01 FS6058-01 FS6058-01 lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl motherboard clock driver motherboard clock driver motherboard clock driver motherboard clock driver ic ic ic ic preliminary information preliminary information preliminary information preliminary information table 8: dc electrical specifications unless otherwise stated, all power supplies = 3.3v 5%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 f rom typical. negative currents indicate current flows out of the device. parameter symbol conditions/description min. typ. max. units overall supply current, dynamic, with loaded outputs i dd f host = 133mhz; all supplies = 3.465v, r iref = 475 ? , i oh = 6 i ref ma supply current, static i dds pwr_dwn# low, all supplies = 3.465v, r iref = 475 ? , i oh = 6 i ref a lvttl digital inputs (pwr_dwn#, mult_0, mult_1, sel_u, sel_a, sel_b, sel_t) high-level input voltage v ih 2.0 v dd +0.3 v low-level input voltage v il v ss -0.3 0.8 v input leakage current i il -5 +5 a pecl reference inputs (pecl_p, pecl_n) high-level input voltage v ih low-level input voltage v il input leakage current i il current reference (iref) bias voltage v oh no load 1.1 v short circuit output source current i oh v o = 0v ma mref_p, mref_n clock outputs (type 5 clock driver) i oh min vdd_m, vdd_r, vdd_66 = 3.135v, v o = 1.0v -33 high level output source current i oh max vdd_m, vdd_r, vdd_66 = 3.465v, v o = 3.135v -33 ma i ol min vdd_m, vdd_r, vdd_66 = 3.135v, v o = 1.95v 30 low level output sink current i ol max vdd_m, vdd_r, vdd_66 = 3.465v, v o = 0.4v 38 ma z ol measured at 1.65v, output driving low 12 55 output impedance z oh measured at 1.65v, output driving high 12 55 ? tristate output current i oz -10 10 a short circuit output source current i osh v o = 0v; shorted for 30s, max. -51 ma short circuit output sink current i osl v o = 3.3v; shorted for 30s, max. 62 ma host_p1:4, host_n1:4 clock outputs (type x1 clock buffer) crossover voltage v x r s = 33.2 ? , r p = 49.9 ? , r iref = 475 ? , i oh = 6 i ref 45 55 %v oh v o = 0.65v, r iref = 475 ? , i oh = 6 i ref 12.9 high-level output source current i oh v o = 0.74v, r iref = 475 ? , i oh = 6 i ref 14.9 ma v dd = 3.30v, over settings in table 4 -7 +7 output source current tolerance ? i oh vdd_i=3.3v5%, over settings in table 4 -12 +12 %i oh output impedance z oh ? v o / ? i o , where v o1 = 1.0v, v o2 = v ss , r iref = 475 ? , i oh = 6 i ref 3000 ? tristate output current i oz -10 10 a
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 6 FS6058-01 FS6058-01 FS6058-01 FS6058-01 lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl motherboard clock driver motherboard clock driver motherboard clock driver motherboard clock driver ic ic ic ic preliminary information preliminary information preliminary information preliminary information table 9: mclk_p, mclk_n clock outputs high drive current (ma) low drive current (ma) voltage (v) min. typ. max. voltage (v) min. typ. max. 0 0 0 0 0 -49 -83 -132 0.2 11 17 24 0.2 -48 -83 -131 0.4 21 32 45 0.4 -48 -82 -130 0.6 30 45 64 0.6 -47 -81 -129 0.8 37 56 79 0.8 -47 -80 -127 1.0 43 65 92 1.0 -46 -79 -126 1.2 47 73 103 1.2 -46 -78 -124 1.4 50 78 112 1.4 -45 -76 -121 1.6 53 82 117 1.6 -43 -74 -117 1.8 54 84 120 1.8 -41 -70 -112 2.0 55 85 121 2.0 -37 -65 -105 2.2 55 85 122 2.2 -33 -59 -97 2.4 55 86 123 2.4 -28 -52 -87 2.6 56 86 123 2.6 -22 -43 -74 2.8 56 86 124 2.8 -14 -32 -60 3.0 56 87 124 3.0 -6 -20 -45 3.2 87 124 3.2 -7 -27 3.4 125 3.4 -7 -150 -125 -100 -75 -50 -25 0 25 50 75 100 125 150 00.511.522.533.5 output voltage (v) output current (ma) 30? 50? 90? data in this table represents nominal characterization data only
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 7 FS6058-01 FS6058-01 FS6058-01 FS6058-01 lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl motherboard clock driver motherboard clock driver motherboard clock driver motherboard clock driver ic ic ic ic preliminary information preliminary information preliminary information preliminary information table 10: ac timing specifications unless otherwise stated, all power supplies = 3.3v, no load on any output, and ambient temperature t a = 25c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 f rom typical. spread spectrum modulation is disabled except for rise/fall time measurements. parameter symbol conditions/description min. typ. max. units overall tristate enable delay * t dzl, t dzh sel_a:b=00, sel133/100#=0 1.0 10 ns tristate disable delay * t dlz, t dhz sel_a:b=11, sel133/100#=0 1.0 10 ns clock stabilization (on power-up) * t stb via pwr_dwn# 3.0 ms host_p1:6, host_n1:6 clock outputs duty cycle * d t ratio of high pulse width to one clock period at v x, r iref = 475 ? , i oh = 6 i ref, r s =33.2 ? , r p =49.9 ? 45 55 % clock skew * t sk(o) host pair to host pair @ v x, r iref = 475 ? , i oh = 6 i ref , r s = 33.2 ? , r p = 49.9 ? 100 ps jitter, additive period (peak-peak) * t j( ? p) rising edge to rising edge at v x,, r iref = 475 ? , i oh = 6 i ref , r s = 33.2 ? , r p = 49.9 ? t j(in) + 100 ps rise time * t r rising edge to rising edge at v x,, r iref = 475 ? , i oh = 6 i ref , r s = 33.2 ? , r p = 49.9 ? 175 450 ps rise/fall time matching* rising edge to rising edge at v x,, r iref = 475 ? , i oh = 6 i ref , r s = 33.2 ? , r p = 49.9 ? 20 % mref_p, mref_n clock outputs duty cycle * d t ratio of high pulse width to one clock period, measured at 1.5v 45 55 % jitter, additive period (peak-peak) * t j( ? p) from rising edge to rising edge at 1.5v, c l =30pf t j(in) + 100 ps t r min measured @ 0.4v ? 2.4v; c l =10pf 0.4 rise time * t r max measured @ 0.4v ? 2.4v; c l =30pf 1.6 ns t f min measured @ 2.4v ? 0.4v; c l =10pf 0.4 fall time * t f max measured @ 2.4v ? 0.4v; c l =30pf 1.6 ns
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 8 FS6058-01 FS6058-01 FS6058-01 FS6058-01 lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl motherboard clock driver motherboard clock driver motherboard clock driver motherboard clock driver ic ic ic ic preliminary information preliminary information preliminary information preliminary information 4.0 package information table 11: 48-pin ssop (0.300") package dimensions dimensions inches millimeters min. max. min. max. a 0.095 0.110 2.41 2.79 a 1 0.008 0.016 0.20 0.41 b 0.008 0.0135 0.20 0.34 c 0.005 0.010 0.13 0.25 d 0.620 0.630 15.75 16.00 e 0.395 0.420 10.03 10.67 e 1 0.291 0.299 7.39 7.59 e 0.025 bsc 0.64 bsc h 0.015 0.025 0.38 0.64 l 0.020 0.040 0.51 1.01 0 8 0 8 e e 1 48 1 american microsystems, inc. b d a 1 seating plane a e c l h 45 table 12: 48-pin ssop (0.300") package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air ja air flow = 0 m/s 93 c/w lead inductance, self l 11 longest lead 5.5 nh l 12 longest lead to any 1 st adjacent lead 3.0 lead inductance, mutual l 13 longest lead to any 2 nd adjacent lead 2.1 nh lead capacitance, bulk c 11 longest lead to v ss 0.94 pf c 12 longest lead to any 1 st adjacent lead 0.46 lead capacitance, mutual c 13 longest lead to any 2 nd adjacent lead 0.05 pf
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 9 FS6058-01 FS6058-01 FS6058-01 FS6058-01 lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl motherboard clock driver motherboard clock driver motherboard clock driver motherboard clock driver ic ic ic ic preliminary information preliminary information preliminary information preliminary information table 13: 48-pin tssop (6.1mm) package dimensions dimensions inches millimeters min. max. min. max. a - 0.047 - 1.20 a 1 0.002 0.006 0.05 0.15 b 0.0067 0.011 0.17 0.27 c 0.0035 0.008 0.09 0.20 d 0.488 0.496 12.40 12.60 e 0.318 bsc 8.10 bsc e 1 0.236 0.244 6.00 6.20 e 0.019 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 s 0.008 - 0.20 - 1 0 8 0 8 2 12 ref 12 ref 3 12 ref 12 ref e 1 american microsystems, inc. e 1 48 be d a 1 seating plane a c l 1 3 2 s table 14: 48-pin tssop (6.1mm) package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air ja air flow = 0 m/s 89 c/w lead inductance, self l 11 longest lead 3.50 nh l 12 longest lead to any 1 st adjacent lead 1.82 lead inductance, mutual l 13 longest lead to any 2 nd adjacent lead 1.17 nh lead capacitance, bulk c 11 longest lead to v ss 0.63 pf c 12 longest lead to any 1 st adjacent lead 0.30 lead capacitance, mutual c 13 longest lead to any 2 nd adjacent lead 0.03 pf
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 10 FS6058-01 FS6058-01 FS6058-01 FS6058-01 lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl lvpecl to hcsl/lvttl motherboard clock driver motherboard clock driver motherboard clock driver motherboard clock driver ic ic ic ic preliminary information preliminary information preliminary information preliminary information 5.0 ordering information table 15: device ordering codes device number ordering code package type operating temperature range shipping configuration 11915-802 48-pin (0.300?) ssop 0 c to 70 c (commercial) tape and reel FS6058-01 11915-202 48-pin (6.1mm) tssop 0 c to 70 c (commercial) tape and reel 6.0 revision information date page description 8/4/00 - this document contains information on a new product. specifications and information herein are subject to change without notice. copyright ? 2000 american microsystems, inc. devices sold by ami are covered by the warranty and patent indemnification provisions appearing in its terms of sale only. ami makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ami makes no warranty of merchantability or fitness for any purposes. ami reserves the right to discontinue production and change specifications and prices at any time and without notice. ami?s products are intended for use in commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by ami for such applications. american microsystems, inc., 2300 buckskin rd., pocatello, id 83201, (208) 233-4690, fax (208) 234-6796, www address: http://www.amis.com e-mail: tgp@amis.com
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